Single event upset immune keeper circuit and method for dual redundant dynamic logic
US7075337B2 · kind B2 · utility
8Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Aug 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00338
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes precharging a first dynamic node, precharging a second dynamic node, and maintaining a first logic state of a signal on the first dynamic node responsive to a second logic state of a signal on the second dynamic node. The method further includes maintaining the second logic state of the signal on the second dynamic node responsive to the first logic state of the signal on the first dynamic node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.