Memory output timing control circuit with merged functions
US7075855B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2005 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Feb 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output timing control circuit for use with a memory array. The output timing control circuit includes a redundancy decode circuit and a bit column output circuit. The bit column output circuit includes a first bit column output gate and a second bit column output gate, each bit column output gate is coupled to a bitline in the memory array. A precharge circuit is coupled to an output of the first bit column output gate and the second bit column output gate. The precharge circuit is responsive to a port enable signal. The redundancy decode circuit receives the port enable signal and a fuse signal and activates one of the first bit column output gate and the second bit column output gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.