Programmable packet processor with flow resolution logic
US7075926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jan 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/503
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable packet switching controller has a packet buffer, a pattern match module, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and to store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The packet classification engine has a decision tree-based classification logic for classifying a packet. Each of the leaves of the tree represents a packet classification. The packet classification engine uses the header data cache index to retrieve the header data to perform multiple header checks, starting at a root of the tree and traversing branches until a leaf has been reached. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed. The sub-engines includ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.