Method and apparatus for evaluating logic states of design nodes for cycle-based simulation
US7076416B2 · kind B2 · utility
16Cited by
15References
23Claims
0Family size
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Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Aug 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.