System bus controller and the method thereof
US7076585B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system bus controller for a computer system and a related method are introduced. The computer system has at least a bus and a bus master electrically connected to the bus. The system bus controller includes a bus slave interface, a master queue, a bus master interface, a queue entries executor and a master queue management unit. Initially, any entry command transmitted over the bus by the bus master will be sequentially queued in a memory. Then, a corresponding acknowledge signal to release access of the bus is generated by the queue management unit. Then, the queued entry commands are sequentially executed to generate corresponding results, which will be caught by the bus master in an active or passive manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.