Buffer management in packet switched fabric devices
US7076587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jan 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/508
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.