Mechanism for on-the-fly handling of unaligned memory accesses
US7076631B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jan 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.