Generating a test sequence using a satisfiability technique
US7076712B2 · kind B2 · utility
4Cited by
5References
43Claims
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Key dates
| Filing date | May 22, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jul 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318502
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Generating a test sequence includes receiving a circuit representation describing a circuit, and a fault associated with the circuit representation. A miter circuit model associated with a good circuit model and a faulty circuit model is established according to the circuit representation. A satisfiability problem corresponding to the fault as associated with the miter circuit model is also established. Whether the satisfiability problem is satisfiable is determined. If the satisfiability problem is satisfiable, a test sequence is generated for the fault as associated with the miter circuit model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.