Functional block design method and apparatus
US7076754B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2003 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Feb 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A functional block design method capable of shortening the period needed for developing functional blocks in compliance with orders. A logic design is prepared for a desired number of memory floor plan blocks with respective predetermined data storage capacities and a fixed block different from the memory floor plan blocks, and block-based design data is created in compliance with the logic design. The created block-based design data is verified in that a constraint on the creation of a CPU macro is always fulfilled within the limits up to which the memory blocks can be mounted. Using the verified block-based design data, design data of a CPU macro functional block in which a desired number of memory blocks corresponding to a desired memory capacity are connected to the fixed block is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.