SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
US7078285B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0174
Abstract
A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer. Silicide layers are formed on the silicon-containing layers, wherein the silicide layer includes nickel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.