High value split poly P-resistor with low standard deviation
US7078305B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Dec 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/403
Abstract
A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. In this invention this layer is arranged to be about 1000 A or less thick. Such a resistor form with this thickness has been shown to demonstrate a better standard deviation of resistance compared to resistors made with a thicker layer. Additionally, practical resistors made in elongated forms demonstrate better standard deviations of resistance when five bends were incorporated into the form. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition that may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact et…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.