Semiconductor memory device having a shallow trench isolation structure

US7078774B2 · kind B2 · utility

Assignees

• Kabushiki Kaisha Toshiba · JP
• Toshiba Microelectronics Corporation · JP

Inventors

• Toshiyuki Kondo
• Katsumasa Hayashi · Yokkaichi, JP
• Tomoya Osaki · Yokohama, JP
• Seishi Irie · Yokohama, JP

Key dates

• Filing date: Dec 22, 2004
• Grant date: Jul 18, 2006
• Expiry date: Dec 31, 2024

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/904

Abstract

A semiconductor memory device includes a cell array having matrix-like arrayed plural SRAMs on a semiconductor substrate having an N-well and P-well. The N-well and the P-well are isolated from each other with an isolation region each having a shallow trench structure. Each memory cell includes two CMOS inverter circuits having input and output nodes making a cross-coupled connection. First and second capacitors are connected between each gate node of two CMOS inverter circuits and the N-well and/or N-well.