PLL loop filter capacitor test circuit and method for on chip testing of analog leakage of a circuit
US7078887B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers. The reference resistor circuit is broken into several series resistors and additional transistors and resistors are supplied with their terminals shorted out, to allow for RIT-B circuit tuning. The output of the test circuit provides the measurement of analog leakage to a digital tester for testing of chips having the c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.