Methodology to accurately test clock to signal valid and slew rates of PCI signals
US7078924B2 · kind B2 · utility
3Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Mar 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.