Buffer memory address translation device
US7079458B2 · kind B2 · utility
2Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2001 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Mar 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
To provide an optical disk drive having an enhanced replaying capability in case of an abnormality occurring in various kinds of synchronization of the optical disk drive or in replay of a defective sector.A frame synchronization counter value address translation decoder 202, low order ID address translation decoder 203, adder/subtracter 204, high order ID address translation decoder 205, and adder 206 are used to translate information read from an optical disk medium into an absolute storage address in a storage medium, and thus data that is highly replayed can be stored in the storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.