Block matching processor and method for block matching motion estimation in video compression
US7079579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2001 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Mar 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/51
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
There is provided a block matching processor and method for flexibly supporting block matching motion estimation at motion vector prediction modes using matching blocks of various sizes. Each of difference unit (D-unit) arrays takes each smallest size matching block, calculates the difference between the pixels of a current frame and the pixels of a reference frame, and converts the differences to absolute values. An accumulator generates SADs (Sum of Absolute Difference) for the smallest size matching blocks and SADs for all the matching blocks of various sizes by tree-like hierarchical addition of the absolute values of the smallest size matching blocks received from the D-unit arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.