Processor with tagging buffer and methods for avoiding memory collisions
US7080231B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2002 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a tagging buffer for storing information that advises the processor of potential memory collisions caused by program instruction pairs that refer to the same memory address. In one method for avoiding memory collisions, a program having tagging code identifying program instruction pairs of the program that refer to a same memory address is compiled. The program instruction pairs in the compiled program code are processed while verifying an order in which the program instruction pairs are to be executed using the compiled tagging code, which is loaded into a tagging buffer. In another method, a program that does not include tagging code is compiled. When a trap occurs in the processing of a program instruction pair, program counters that cause the instructions to be executed in a desired order are added to a tagging buffer. A computer system including the processor also is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.