Method and apparatus for interface failure survivability using error correction
US7080288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | May 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.