Method for testing jitter tolerance of high speed receivers
US7080292B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
Inventors
Key dates
| Filing date | Apr 9, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.