Verifying logic synthesizers
US7080333B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Oct 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and code for verifying that modifications or improvements to a synthesizer algorithm do not introduce errors. Specifically, a number or VHDL or Verilog models are chosen. Two netlists are then synthesized from each modeled circuit, once using a unmodified or trusted synthesizer, and once using the modified or improved synthesizer. For each circuit, a set of input test vectors are generated. These vectors are somewhat random in nature, but modified or generated intelligently using knowledge about the circuit to be testing. For each circuit, each netlist is simulated, generating a set of output vectors. These output vectors are compared. If the output vectors match each other for each of the circuits tested, there is a high probability that the improved or modified synthesizer is not introducing new errors into the netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.