Automatic clock gating insertion in an IC design
US7080334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jan 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design, the method comprising: identifying a sequential element associated with a feedback loop in the design; producing a feedback loop signature associated with the feedback loop; wherein the signature includes an indication of feedback element instance type for each feedback element instance in the feedback loop, feedback position at each instance of a feedback element type in the feedback loop and a control signal for each instance of a feedback element type in the feedback loop; evaluating the feedback loop signature so as to generate associated stimulus logic; generating associated load logic; and inserting the generated stimulus logic to control a clock input to the sequential element; and inserting the generated load logic to provide a data input to the sequential element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.