Plane representation of wiring in a design layout
US7080339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Jun 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the invention provide a method of specifying routes in a design layout, where each route has a set of segments and each segment has a shape. The method receives a route, and for each segment of the received route, identifies n half planes that when intersected provide the shape of the segment. In some embodiments, n is an integer greater than 4. Some embodiments provide a method of generating a representation of a route formed by several adjoining polygons. For each polygon, this method (1) identifies a direction for the polygon, (2) defines a segment along the identified direction, where the segment has a starting point and an ending point, and (3) identifies more than four values that specify more than four half planes in conjunction with the starting and ending points of the segment, where the intersection of the specified half planes provides the shape of the polygon. Some embodiments provide a design layout that has several routes that are each represented by a set of segments. Each particular segment has an associated shape, which is specified by a data-storage index for the particular segment. Each particular data-storage index identifies a particular set…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.