Interconnect-aware integrated circuit design
US7080340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Mar 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided. The environment terminal 36 comprises a connection to the model 35 via at least one circuit component representing the effect of the crossing line on the model. The environment terminal 36 is connected to the appropriate crossing line in the integrated circuit design, whereby crossi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.