Method of forming a conductive pattern of a semiconductor device and method of manufacturing a non-volatile semiconductor memory device using the same
US7081380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2004 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Apr 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.