Wafer-based ion traps
US7081623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2003 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Jul 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J49/0018
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus for an ion trap includes a semiconductor or dielectric wafer with front and back surfaces, a sequence of alternating conductive and dielectric layers formed over said front surface, and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a substantially right cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.