Semiconductor integrated circuit device for preventing warping of an insulating film therein
US7081681B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2003 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Apr 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By having substantially narrow pitches between wires in a first wiring layer located in an interlayer insulating layer of a semiconductor integrated circuit device, a total amount of the first wiring layer in the interlayer insulating film may be increased, thereby reducing a total amount of the interlayer insulating film having low hardness, which causes warping. As a result, stresses that are typically applied on a protective film of the semiconductor integrated circuit device due to the warping may be prevented. This may prevent the occurrence of a crack, etc. in the protective film. Therefore, it may be possible to prevent failures such as electrical disconnection of a second wiring layer above the protective film due to the crack in the protective film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.