Method and apparatus for generating and controlling a multiphase clock
US7081783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2005 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Apr 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiphase clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as an M-clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted M-clock divided by M. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have a 180°/M relative phase difference. A halt circuit controls the halt multiplexer control to select the gated generated clock when a selected recovered clock matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.