Process for fabrication of a liquid crystal display with thin film transistor array free from short-circuit
US7081930B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Feb 23, 2004 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Feb 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Pixels of a liquid crystal display are laid on a delta pattern, and short-circuit is liable to take place between a source layer and a drain layer and/or between a gate layer and a storage electrode layer, wherein a contact slit is formed in a gate insulating layer intervening between the gate/storage electrode layers and the source/drain layers in such a manner as to break a piece of residual amorphous silicon and make a piece of residual metal exposed thereto, and the piece of residual metal is broken during a patterning step for the source/drain layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.