Ferroelectric memory input/output apparatus
US7082047B2 · kind B2 · utility
97Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | May 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.