Synchronous dynamic register updating across a distributed system
US7082127B1 · kind B1 · utility
3Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Jun 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5627
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switch for a network. The switch comprises a memory mechanism in which portions of packets are stored. The switch comprises a mechanism for instituting changes to the memory mechanism while the memory mechanism continuously operating on packets. A method for switching packets. The method comprises the steps of receiving changes for a memory mechanism of a switch at a buffer of the switch. Then there is the step of implementing the changes to the memory mechanism when the memory mechanism receives an implementation signal while the memory mechanism continuously operates on packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.