System and method for instruction level multithreading scheduling in a embedded processor
US7082519B2 · kind B2 · utility
64Cited by
34References
26Claims
0Family size
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Key dates
| Filing date | Oct 1, 2002 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Apr 17, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.