Power management using processor throttling emulation
US7082542B2 · kind B2 · utility
15Cited by
2References
35Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a processor state of a processor is determined upon expiration of a system management interrupt (SMI) timer. The processor state is one of an operational state and a low power state. The SMI timer is loaded with a timer value based on the processor state. The timer value is one of a first value and a second value. The processor is transitioned to one of the operational state and the low power state according to the processor state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.