System and method of detecting a bit processing error
US7082556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Aug 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/203
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiver circuitry. Data generated by a BERT is transmitted in an electrical form to a DUT and a master device. The DUT transmits data received in an electrical form to the master device in an optical form and the master device transmits data received in an electrical form to the DUT in an optical form. The master device and the DUT then transmit data received in an optical form back to the BERT in an electrical form. The data received from the DUT and the master device, respectively, is separately tested for bit errors. Do so enables to calculation of bit error rates for two distinguishable data paths through the DUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.