High speed serial interface test
US7082557B2 · kind B2 · utility
70Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Sep 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/42
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.