Schematic driven placement method and program product for custom VLSI circuit design
US7082595B1 · kind B1 · utility
7Cited by
3References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Jul 25, 2006 |
| Priority date | — |
| Expiry date | Feb 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition of cell physical position in the horizontal direction, a definition of the cell's vertical stacking level, a definition of the cell orientation, a specification of vertical alignment of multiple cell instances, and a definition of vertical spacing between 2 adjacent cell instances. These input parameters are used to generate a layout with the placed circuit elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.