Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories

US7084032B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Barbara Crivelli · Milano, IT
• Mauro Alessandri · Vimercate, IT

Key dates

• Filing date: Jan 30, 2003
• Grant date: Aug 1, 2006
• Expiry date: Jan 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02271
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.