Load resistor with dummy contact substantially free of charge build up during etching process
US7084478B2 · kind B2 · utility
5Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2002 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Apr 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
Abstract
A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.