Packaged semiconductor device and method of manufacture using shaped die
US7084488B2 · kind B2 · utility
4Cited by
16References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2002 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor packaging technique provides for a semiconductor device with improved electrical and thermal performance. According to one embodiment of the invention, die edges are shaped before encapsulation to move the peripheral area of the die, which is more susceptible to stress and cracking, further inside the molding compound. This results in a device that can better withstand stress as well being more resistant to corrosion and other reliability problems caused by environmental conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.