Parallel bus debugging tool
US7084618B2 · kind B2 · utility
0Cited by
7References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Oct 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for testing the signals on a parallel communication bus uses a single printed circuit board that connects to the bus. The signals from the bus may be passively and actively filtered prior to a multiplexer. The multiplexer may be controlled by a variety of inputs, including communications over a second bus by a remote device. The output of the multiplexer is one or more probe points that may be connected to a measurement device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.