Background calibration of pipelined ADCs using flow control
US7084804B1 · kind B1 · utility
3Cited by
3References
15Claims
0Family size
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Key dates
| Filing date | Jul 13, 2005 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A modified pipeline architecture allows the simple implementation of a foreground calibration technique with the continuous calibration benefits of the background calibration techniques. To calibrate a stage in the pipeline, a calibration voltage is presented to the input instead of the output from the previous stage. To prevent loss of information, the output data of the previous stage is passed on to a stage further down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.