On-chip power-on voltage initialization
US7085176B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Apr 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured to store the predetermined values on the nodes of the memory array in response to successive enablement of word lines corresponding to the nodes of the memory array and automatic reset of the word lines. Circuitry included for initializing control and data signals of the memory array are effectively disabled upon termination of the initialization. Inclusion of circuitry that initiates and terminates the initialization obviates an additional input/output pin for this purpose.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.