Delayed bitline leakage compensation circuit for memory devices
US7085184B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Nov 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delayed bitline leakage compensation circuit for memory devices is disclosed. The delayed bitline leakage compensation circuit includes a bitline leakage model circuit for modeling discharge of a bitline by leakage current in a read operation. It further has a delayed charge signal generator for generating a delayed charge signal in response to the bitline leakage model circuit discharging to approximately a discharge threshold. The delayed charge signal generator is deactivated if the bitline is discharged by a selected memory cell. Moreover, the delayed bitline leakage compensation circuit includes a delayed charge circuit for charging the bitline in response to the delayed charge signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.