System and method for identifying semiconductor process steps for queue-time control and abnormality detection
US7085612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jan 4, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A computer-implemented method and system for identifying process steps for purposes of queue-time control and abnormality detection is provided. In one example, the method includes retrieving manufacturing information associated with a fabrication process, where the manufacturing information includes multiple process step pairs. The manufacturing information may be divided into at least a high group and a low group using a statistical clustering method. Values, such as P-values, may then be calculated for each process step pair by applying a non-parametric statistical method to the high and low groups. The process step pairs may be ranked based on their calculated values, and redundant process step pairs may be eliminated. The remaining process step pairs may then be analyzed to identify a particular process step or process step pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.