Size reduction techniques for vital compliant VHDL simulation models
US7085701B2 · kind B2 · utility
15Cited by
12References
32Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jun 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.