Low power vector summation method and apparatus
US7085794B2 · kind B2 · utility
3Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2002 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Nov 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49994
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.