Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption
US7085941B2 · kind B2 · utility
87Cited by
4References
8Claims
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Key dates
| Filing date | Apr 16, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jul 18, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock control apparatus for a memory controller comprises an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller. A power-saving control unit controls both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied from the interface unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.