Method and related apparatus for locking phase with estimated rate modified by rate dithering
US7085949B2 · kind B2 · utility
12Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Sep 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and related apparatus for providing a clock synchronized with an input signal. The method includes generating an estimated rate according to transitions in the input signal, processing a dithering step for updating the estimated rate by multiplying it with a predetermined ratio, and adjusting the frequency of the clock according to the updated estimated rate. The predetermined ratios used in repeated dithering steps are modified according to a predetermined rule such that the predetermined ratio is different when the dithering steps are repeated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.