Dynamic test program generator for VLIW simulation
US7085964B2 · kind B2 · utility
4Cited by
3References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | May 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.