Method of optimizing RTL code for multiplex structures
US7086015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2004 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.