Method and apparatus for verifying logical equivalency between logic circuits
US7086016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Feb 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.